In the middle of the twentieth century, comic strip detective Dick Tracy was famous for his two-way wrist radio. Comic strip readers probably considered that radio a fanciful invention of science fiction. Today, cellular telephones, wireless Internet connections, keyless automobile control, wireless game controllers, and many other everyday wireless devices have features that Dick Tracy would not have imagined. Today's wireless devices require small, low-cost integrated circuit transmitters, and they often use sophisticated methods of controlling the power output of the transmitter, for extending battery life and for transmitting data. They also need to work across different wireless standards and multiple frequency bands.
Modulation is the process of combining analog or digital data with a carrier signal for transmission. FIG. 1 illustrates a conceptual view of a modulator 100.
In operation, modulator 100 combines an information signal 102 with a carrier signal 104 to create a modulated carrier signal 106. Carrier signal 104 is often a radio frequency (RF) signal, but other carrier signals are possible. For example, the carrier signal could be coherent light from a laser.
FIG. 2 illustrates a conventional transmitter 200 with quadrature amplitude modulation (QAM). QAM is a method of sending two information signals on one carrier.
As illustrated in FIG. 2, transmitter 200 comprises a digital-to-analog converter (DAC) 204, a low pass filter 206, a local oscillator 208, a multiplier 210, a DAC 214, a low pass filter 216, a local oscillator 218, a multiplier 220, an adder 222, a variable gain amplifier (VGA) 224, a VGA 226, an impedance matching device 228 and a load 230. Load 230 could, for example, be an antenna or a power amplifier.
DAC 204 is arranged to receive I-Data 202 and to output a signal 232. Low pass filter 206 is arranged to receive signal 232 and output a signal 234. Local oscillator 208 is arranged to provide a carrier signal 236. Multiplier 210 is arranged to receive single 234 and carrier signal 236 and to output a signal 238.
DAC 214 is arranged to receive I-Data 212 and to output a signal 213. Low pass filter 216 is arranged to receive signal 213 and output a signal 247. Local oscillator 218 is arranged to provide a carrier signal 245. Multiplier 220 is arranged to receive signal 247 and carrier signal 245 and to output a signal 248.
Adder 222 is arranged to receive signal 238 and signal 248 and to output a signal 240. VGA 224 is arranged to receive signal 240 and to output a signal 242. VGA 226 is arranged to receive signal 242 and output a signal 244. Impedance matching device 228 is arranged to receive signal 244 and output a signal 246. Load 230 is arranged to receive signal 246 and is connected to ground.
In operation, local oscillators 208 and 218 both operate at the same carrier frequency at which transmitter 200 will be operating. Carrier signal 236 provided by local oscillator 208 is in quadrature with carrier signal 245 provided by local oscillator 218, meaning that carrier signals 236 and 245 have the same frequency but differ in phase by 90°. DAC 204, low pass filter 206 and multiplier 210 make up an in-phase leg of transmitter 200. DAC 214, low pass filter 216, oscillator 218 and multiplier 220 make up a quadrature leg of transmitter 200.
DAC 204 converts I-Data 202 data from digital to analog. Low pass filter 206 removes high frequency quantization noise from signal 232. Multiplier 210 multiplies signal 234 with carrier signal 236 to create signal 238, which is carrier signal 236 modulated by signal 234.
DAC 214 converts Q-Data 212 data from digital to analog. Low pass filter 216 removes high frequency quantization noise from signal 213. Multiplier 220 multiplies signal 247 with carrier signal 245 to create signal 248, which is carrier signal 245 modulated by signal 247.
Adder 222 creates signal 240 by adding signals 238 and 248. Signal 240 is amplified by VGA 224. Signal 242 is amplified by VGA 226. Both VGA 224 and VGA 226 provide gain control in the form of amplification or attenuation.
Transmitter 200 has several problems. If, for example, transmitter 200 is implemented as a conventional CMOS integrated circuit, many current-to-voltage and voltage-to-current conversions are required as signals move from the output of one functional block to the input of the next functional block. For example, a current-to-voltage conversion would be required at DAC 204 output, while low pass filter 206 needs to convert signal 234 from an input voltage to an input current. The input current needs to be converted to a voltage at the output of low pass filter 206 as signal 234. Current-to-voltage and voltage-to-current conversions introduce undesirable nonlinearities. These conversions also cause undesirable increases in power consumption and in noise, and these conversions have the undesirable side effect of increasing the number of devices needed in the integrated circuit.
If transmitter 200 is implemented in a technology other than bipolar transistors, problems arise in adjusting the gain of VGA 224 and VGA 226.
FIG. 3 illustrates a conventional system 300 used to control the gain of a VGA in a conventional transmitter.
System 300 includes a linear to exponential converter 302 and a bipolar VGA 304. Converter 302 is arranged to receive a linear control voltage 306 and to output an exponential signal 308. Bipolar VGA 304 is arranged to receive an input signal 310 and output an amplified or attenuated signal 312.
In operation, converter 302 performs the mathematical function of taking the exponential value of linear control voltage 306. Exponential signal 308 is exponentially related to linear control voltage 306. Exponential signal 308 is used to control the gain of VGA 304.
Because the collector current of a bipolar transistor is exponentially related to the base-to-emitter voltage, converter 302 can be easily implemented with a bipolar transistor. In other technologies, however, a linear to exponential converter similar to 302 cannot be easily implemented.
The gain control of system 300 will now be described with reference to FIG. 4.
FIG. 4 is a graph, wherein the x-axis corresponds to linear control voltage 306, and the y-axis is the output power of VGA 304. Arbitrary x-axis values are shown going from 0 to 1023 because it is assumed, for purposes of example, that linear control voltage 306 is provided by a 10-bit digital-to-analog converter. The y-axis units are dBm. The dBm scale is a logarithmic scale in which 1 milliwatt is taken as zero. A power P, in milliwatts, can be expressed as 10 log (P) dBm.
A line 402 in FIG. 4 is a straight line because the dBm scale is a logarithmic scale and because the output power from VGA 304 is proportional to the exponential of linear control voltage 306. This linear relationship between linear control voltage 306 and output power from VGA 304, expressed in dBm, is the desired relationship for transmitter 200.
FIG. 5 illustrates an example of a CMOS VGA circuit 500 using a conventional method for controlling power output.
As illustrated in FIG. 5, CMOS VGA circuit 500 includes NMOS FETs 502, 504, 506, 508, 510 and 512. CMOS VGA circuit 500 is connected to a center-tapped load 514.
The gates of FETs 502 and 512 are connected to a control voltage VON 516. The gates of FETs 504 and 510 are connected to a control voltage V1 528. The gates of FETs 506 and 508 are connected to a control voltage V2 530. FETs 502 and 512 are each a single PET. Although FETs 504, 506, 508 and 510 are each illustrated as a single PET, each of FETs 504, 506, 508 and 510 is an arrangement of multiple (100 in this example) FETs. The number of FETs depend on the total desired gain control range.
Control voltage VON 516 is at its maximum value whenever CMOS VGA circuit 500 is operational. When control voltage V1 528 is at its maximum value and control voltage V2 530 is at zero volts, no current flows through FET 506. In this case, a current I0+ 524 is equal to a current IRF+ 526. Similarly, when control voltage V1 528 is at its maximum value and control voltage V2 530 is at zero volts, no current flows through PET 508. In this case, a current I0− 532 is equal to a current IRF− 534.
Further, when control voltage V1 528 is at its maximum value and control voltage V2 530 is zero. CMOS VGA circuit 500 provides maximum power to load 514. FET 504, which is controlled by control voltage V1 528, is an arrangement of 100 FETs and FET 506, which is controlled by control voltage VON 516, is a single FET. So when control voltage V1 528 is at its maximum value and control voltage V2 530 is at zero volts, 101 FETs are providing gain. If FET 502 and each device within FET 504 have a transconductance of Gm, the total transconductance is 101Gm.
To begin decreasing the power delivered to load 514, control voltage V2 530 is increased. When control voltage V2 530 reaches its maximum value, current IRF+ 526 splits up among FETs 502, 504 and 506. Because FETs 504 and 506 are, in actuality, each 100 FETs, the current division is such that 100/201 of current IRF+ 526 flows in a path 520 through FET 504, another 100/201 of the current flows in a path 522 through FET 506 and 1/201 of the current flows in a path 518 through FET 502.
Because of the symmetry of CMOS VGA circuit 500, similar current division occurs for IRF− 534. This means that 101/201 of the current now flows through load 514. The other 100/201 of the current now flows in path 522 through FET 506 and in path 536 through FET 508. This means that when control voltage V2 530 reaches its maximum value, the current delivered to load 514 is about ½ of the maximum possible current. This change in current corresponds to a change in power of about 6 dB because the power is proportional to the square of the current.
As shown in FIG. 4, output changes of much more than 6 dB are needed, but changing control voltage V2 530 from zero to its maximum value causes a change of only about 6 dB. Further changes in power output require changing control voltage V1 528.
For CMOS VGA circuit 500, changing control voltage V2 530 from zero to its maximum value results in a decrease in output power of only 6 dB. Further decreases in output power require a decrease in control voltage V1 528. To decrease power by much more than 6 dB, most of the decrease in output power will have to come from decreasing control voltage V1 528.
If all of the FETs in CMOS VGA circuit 500 were turned OFF, I0+ 524, IRF+ 526, I0− 532 and IRF− 534 would, in theory, all be zero. Because the FETs in CMOS VGA circuit 500 are not ideal, their leakage will cause this minimum value to be nonzero and not well-controlled. Because this current is not well-controlled, VON 516 is always kept at its maximum value. The minimum value of I0+ 524 then occurs when FET 504 is turned OFF and FET 506 is fully ON. Similarly, the minimum value of I0− 532 occurs when FET 510 is turned OFF and FET 508 is fully ON. Since FETs 502 and 512 are single FETs but FETs 506 and 508 are, in fact, each an arrangement of 100 FETs, the minimum possible current through load 514 is 1/101 of the maximum possible current. The minimum possible current of about 1/100 of the maximum possible current corresponds to a power difference, from a maximum to a minimum power, of about 40 dB.
In CMOS VGA circuit 500, varying control voltage V2 530 through its entire range results in a power change of 6 dB. As discussed above, the total power range of the circuit is about 40 dB. Of this 40 dB, about 34 dB conies from varying control voltage V1 528. This means that a linear relationship, like one shown in FIG. 4, cannot be obtained with CMOS VGA circuit 500.
FIG. 2 shows a conventional transmitter and FIG. 5 shows a conventional method of controlling the gain when an amplifier in the conventional transmitter is not implemented with bipolar transistors and is, for example, implemented in CMOS. As explained above, voltage-to-current and current-to-voltage conversions in transmitter 200 cause many undesirable results. Also as explained above, the conventional gain control method of FIG. 5 does not give the desired gain curve shown in FIG. 4.
What is needed is a transmitter that eliminates the undesirable results caused by voltage-to-current and current-to-voltage conversions and that also provides a gain curve similar to the one shown in FIG. 4.